The present invention relates to an output circuit and an input circuit, and more particularly, it relates to an output circuit and an input circuit that can apply to a small amplitude interface circuit used in a signal transmission system between integrated circuits.
In recent years, in consequence of the high send and receive speed of a binary signal between CMOS (complementary metal-oxide semiconductor) integrated circuits, signals at a well-known TTL or CMOS level which has been conventionally used are becoming difficult to send and receive. In the TTL or CMOS level, the frequency of about several tens of MHz is a limit, and when the frequency exceeds the limit, a small amplitude interface circuit, which uses a transmission signal having a smaller voltage amplitude than the TTL and CMOS levels, is used. The small amplitude interface circuit implements high-speed signal transmission by performing the impedance matching of a transmission line, reducing electrical reflection and shortening the charge and discharge time generated in the capacitance component inside the circuit due to the small amplitude of the transmission signal voltage.
As the typical conventional typical small amplitude interface circuit, for example, there are interface circuits based on CTT and GTL (Gunning transceiver logic). Further, as the transmission methods of the conventional small amplitude interface circuits, there are an unbalanced transmission-type method and a balanced transmission-type method. Because the unbalanced transmission type interface circuit has a configuration in which transmission signals are transmitted via a single transmission line, it has such advantages that the configuration is simple and the number of pins used for the application of an LSI (large scale integrated circuit) can be reduced. Conversely, because the balanced transmission-type interface circuit has a configuration in which transmission signals are transmitted via two transmission lines and use differential signals, it has such advantages that noise can be offset and relative transmission amplitude can be increased.
Up to this time, as an output circuit and an input circuit that can apply to the small amplitude interface circuit based on the CTT, for example, there are those that have been disclosed in the xe2x80x9cCenter-Tap-Terminated (CTT) Low-Level, High-Speed Interface Standard for Digital Integrated Circuits, JEDEC STANDARD, JESD8-4xe2x80x9d.
Further, as an input circuit that can apply to other conventional small amplitude interface circuits, there are those that can apply to the GTL disclosed in xe2x80x9cA CMOS Low-Voltage-Swing Transmission-Line Transceiver, by Bill Gunning, et al, ISSCC Digest of Technical Papers, pp. 58-59, February 1992xe2x80x9d.
Because the conventional output circuit and input circuit are described in these references, their detailed description is not redundantly described in this specification.
However, in the small amplitude interface circuit based on the balanced transmission type CTT, the amplitude of an output signal sent to the transmission line between the output circuit and the input circuit is small. Therefore, as the input circuit, a differential amplification circuit having the capability to receive a small amplitude signal must be used. For example, in the conventional reference (JEDEC STANDARD) with reference to the CTT, a differential amp used as an input circuit whose amplitude of an output signal is about 1.0 V and whose minimum receivable amplitude is 0.2.
On the one hand, in a small amplitude interface circuit, the potential fluctuation of a signal that is propagated via the transmission line needs to be considered due to the fluctuation characteristics of an output circuit, the noise of a transmission signal or the attenuation of a signal, which is being propagated. Therefore, the receiving sensitivity of the input circuit must have a certain tolerance to accommodate the potential (hereinafter referred to as xe2x80x9coutput voltagexe2x80x9d) of an output signal output from the circuit.
Consequently, an input circuit is requested for performing a receiving operation with an ample allowance for a small amplitude input signal and must apply an exceedingly high-performance differential amplification circuit. However, using such high-performance differential amplification circuit is not easy in consideration of circuit technology and cost, and finally, under the present conditions, the light receiving sensitivity of the input circuit cannot have an ample allowance.
Further, in the conventional balanced transmission type interface circuit based on the CTT, the output voltage of an output circuit is determined according to the ratio of the impedance of a terminating resistor in the transmission line and the on (dynamic) resistance of an MOS transistor comprising the output circuit. That is to say, the output voltage of the output circuit greatly affects the operating resistance of the MOS transistor comprising the output circuit.
Therefore, for example, when the resistance of the MOS transistor comprising the output circuit is fluctuated according to the completion of a process, the fluctuation of a power supply voltage or the fluctuation of ambient temperature, the voltage of an output signal is greatly restored to a design value. In a small amplitude interface circuit, fluctuation of such output voltage reduces the allowance for the receiving sensitivity of an input circuit and in the worst case, may cause a malfunction.
Up to this date, to prevent the possibility of such a malfunction, a manufactured integrated circuit is inspected as to whether an output voltage is within the specification value, and if a fluctuation is out of the specification value, the manufactured integrated circuit is discarded as a defective product. Naturally, having many defective products is not desirable because they are not economical. In particular, because an LVDS interface circuit that is a type of a small amplitude interface circuit with a strict specification of the output voltage requirements, a large number of defective products may be generated in the integrated circuit if the conventional output circuit is used.
Further, in a small amplitude interface circuit, because the amplitude of an input signal is small, a differential amp is generally used in the input circuit. However, the conventional input circuit has the configuration in which only two NMOS transistors receive the input signal or only two PMOS transistors receive the input signal. Therefore, in the configuration in which only the NMOS transistors receive the input signal, if the reference potential is in the vicinity of the GND (ground) potential or the potential of a differential input signal is in the vicinity of the GND potential, a sufficient bias voltage between the gate and source of both the NMOS transistors cannot be sufficiently obtained. Furthermore, in the configuration in which only the PMOS transistors receive the input signal, if the reference potential is in the vicinity of power supply potential or the potential of the differential input signal is in the vicinity of power supply potential, the sufficiently bias voltage between the gate and source of both the PMOS transistors cannot be obtained sufficiently.
That is to say, the conventional input circuit can anticipate a full operation only for the input signal in a narrow range, but cannot receive the differential input signal in a broad range. Consequently, the requirements of the LVDS input voltage cannot be satisfied or is extremely difficult to satisfy. Further, it is difficult for the conventional input circuit to support various interface circuits when the specifications of the potential of the input signal differs from an input circuit. Therefore, the input circuit may need to be redesigned in accordance with the specifications, and that is not economical.
Furthermore, the conventional input circuit fluctuates the center potential of the differential input signal by the fluctuation of an input signal, reference potential, a power supply voltage or GND potential, in particular, by the fluctuation of the power supply potential and GND potential; thus, may cause a malfunction.
The present invention anticipates of the problems of the conventional output circuit, and one object is to provide a new and improved output circuit which can secure a fixed allowance for the receiving sensitivity of an input circuit when it is applied to an interface by suppressing the fluctuation of an output voltage and being able to output a fixed output voltage. Another object of the present invention is to provide an economical, new and improved output circuit which is less prone to malfunction in addition to reduce defective products during shipment of applied integrated circuits are shipped.
To solve the issues of the conventional output circuit, an output circuit of the present invention comprises an input terminal receiving an input logical signal, a first output terminal outputting a first output logical signal having a logic corresponding to a logic of the input logical signal, a second output terminal outputting a second output logical signal having a logic corresponding to an inverted logic of the input logical signal, a first constant voltage supply circuit generating a first voltage level, a second constant voltage supply circuit generating a second voltage level, and an output logic formation circuit connected to said first and second constant voltage supply circuits. The output logic formation circuit generates the first and second output logical signals having either the first voltage level or second voltage level based on the logic of the input logical signal.